92706 / 42406 ms ot b8-6166 no.a0251-1/10 LA75694M overview the LA75694M is a pal/ntsc split support vif/sif for hi -fi signal-processing ic that makes the minimum number of adjustments possible. the system is designed so that vco adjustment makes aft adjustment unnecessary, thus simplifying the adjustment steps in endproduct manufacturing. pll detection is adopted in the fm detector, allowing the LA75694M to support multichannel detection for the audio signal. in addition, it also incorporates a buzz canceller that suppresses nyquist buzz for improved audio quality. functions ? vif block: vif amplifier, buzz canceller, bnc, pll detector, if agc, rf agc, aft, equalizer amplifier ? 1st sif block: 1st sif amplifier, 1st sif detector, agc ? sif block: hpf, mix, 500kosc specifications maximum ratings at ta = 25 c parameter symbol conditions ratings unit maximum supply voltage v cc max 6 v circuit voltage v 13 , v 17 v cc v i 6 -3 ma circuit current i 10 -10 ma ta 50 c, independent ic 420 mw allowable power dissipation pd max mounted on a board. ? 720 mw operating temperature topr -20 to +70 c storage temperature tstg -55 to +150 c ? when mounted on a 65 72 1.6mm 3 paper phenol board. recommended operating conditions at ta = 25c parameter symbol conditions ratings unit recommended supply voltage v cc 5 v operating voltage v cc op 4.5 to 5.5 v orderin g number : ena0251 monolithic linear ic for use in tv/vtr applications if signal processing (vif/sif for hi-fi) any and all sanyo semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. consult with your sanyo semiconductor representative nearest you before using any sanyo semiconductor products described or contained herein in such applications. sanyo semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor products described or contained herein.
LA75694M no.a0251-2/10 electrical characteristics at ta = 25c, v cc = 5v, fp = 45.75mhz vif block ratings parameter symbol conditions min typ max unit circuit current i 5 38 45 51.8 ma maximum rf agc voltage v 14 h v cc -0.5 v cc v minimum rf agc voltage v 14 l 0 0.5 v input sensitivity v i s1 = off 27 33 39 db v agc range gr 53 58 db maximum allowable input v i max 90 96 db v no-signal video output voltage v 6 2.1 2.4 2.7 v sync. signal tip voltage v 6 tip 0.7 1.0 1.3 v video output level v o 0.95 1.1 1.25 vp-p black noise threshold voltage v bth 0.5 0.8 1.1 v black noise clamp voltage v bcl 1.2 1.5 1.8 v video s/n s/n 48 52 db c-s best ic-s 38 43 db frequency characteristics fc 6mhz -3 -1.5 db differential gain dg 3 6.5 % differential phase dp 3 5 c no-signal aft voltage v 13 2.0 2.5 3.0 v maximum aft voltage v 13 h 4.0 4.4 5.0 v minimum aft voltage v 13 l 0 0.18 1.0 v aft detection sensitivit y sf 14 21 28 mv/khz vif input resistance r i 45.75mhz 1.5 k ? vif input capacitance c i 45.75mhz 3 pf apc pull-in range (u) fpu 0.7 1.5 mhz apc pull-in range (l) fpl -2.0 -1.4 mhz aft tolerance frequency 1 ? fa1 -200 0 200 khz vco1 maximum variable range (u) dfu 1.0 1.5 mhz vco1 maximum variable range (l) dfl -2.0 -1.4 mhz vco control sensitivity 1.2 3.2 5.0 khz/mv synchronization ratio v s 25.0 28.5 31.5 % 1st sif block ratings parameter symbol conditions min typ max unit conversion gain v g 27 33 39 db 4.5mhz output level s o 53 115 180 mvrms 1st sif maximum input s i max 8 16 mvrms 1st sif input resistance r i (sif) 41.25mhz 2 k ? 1st sif input capacitance c i (sif) 41.25mhz 3 pf sif converter ratings parameter symbol conditions min typ max unit conversion gain v g (sif) 8 11 14 db maximum output level v max 103 109 115 db v carrier suppression ratio v gr (4.5) 15 21 db oscillator level v osc 35 70 mvp-p osc leakage osc leak 14 25 db oscillator stop current i 4 300 a
LA75694M no.a0251-3/10 package dimensions unit : mm 3112b pin assignment 1 12 13 24 12.5 0.63 7.6 5.4 0.15 1.0 0.35 (0.75) 1.7max 0.1 (1.5) sanyo : mfp24s(300mil)
LA75694M no.a0251-4/10 block diagram and ac charac teristics test circuit input impedance test circuit
LA75694M no.a0251-5/10 test conditions v1. circuit current [i 5 ] (1) internal agc (2) input a 45.75mhz 10mvrms continuous wave to the vif input pin. (3) rf agc vr max (4) connect an ammeter to the v cc and measure the incoming current. v2.v3. maximum rf agc voltage, minimum rf agc voltage [v 14 h, v 14 l] (1) internal agc (2) input a 45.75mhz 10mvrms continuous wave to the vif input pin. (3) adjust the rf agc vr (resistor value max.) and measure the maximum rf agc voltage. f (4) adjust the rf agc vr (resistor value min.) and measure the minimum rf agc voltage. f v4. input sensitivity [v i ] (1) internal agc (2) fp = 45.75mhz 400hz 40% am (vif input) (3) turn off the s1 and put 100k ? through. (4) vif input level at which the 400hz detection output level at test point a becomes 0.35vp-p. v5. agc range [gr] (1) apply the v cc voltage to the external agc, if agc (pin 17). (2) in the same manner as for the v4 (input sensitivity), measure the vif input level at which the detection output level becomes 0.35vp-p. vil (3) gr = 20log db v6. maximum allowable input [v i max] (1) internal agc (2) fp = 45.75mhz 15khz 78% am (vif input) (3) vif input level at which the detection output level at test point a is video output (v o ) 1db. v7. no-signal video output voltage [v 6 ] (1) apply the v cc voltage to the external agc, if agc (pin 17). (2) measure the dc voltage of video output (a). v8. sync. signal tip voltage [v 6 tip] (1) internal agc (2) input a 45.75mhz 10mvrms continuous wave to the vif input pin. (3) measure the dc voltage of video output (a). v9. video output level [v o ] (1) internal agc (2) fp = 45.75mhz 15khz 78% am v i = 10mvrms (vif input) (3) measure the peak value of the detection output level at test point a. (vp-p) vil v i
LA75694M no.a0251-6/10 v10.v11. black noise threshold level and clamp voltage [v bth , v bcl ] (1) apply dc voltage to the external agc, if agc (pin 17) and adjust the voltage. (2) fp = 45.75mhz 400hz 40% am 10mvrms (vif input) (3) adjust the if agc (pin 17) voltage to operate the noise canceller. measure the v bth , v bcl at test point a. v12. video s/n [s/n] (1) internal agc (2) fp = 45.75mhz cw = 10mvrms (vif input) (3) measure the noise voltage at test point a in rms volts through a 10khz to 4mhz band-pass filter. noise voltage (n) (4) s/n = 20log = 20log (db) v13. c/s beat [ic-s] (1) apply dc voltage to the external agc if agc (pin 17) and adjust the voltage. (2) fp = 45.75mhz cw; 10mvrms fc = 42.17mhz cw; 10mvrms ? 10db fs = 41.25mhz cw; 10mvrms ? 10db (3) adjust the if agc (pin 17) voltage so that the output level at test point a becomes 0.72vp-p. (4) measure the difference between the levels for 3.58mhz and 0.92mhz components at test point a. video portion (vp-p) noise voltage (vrms) 1.12vp-p noise voltage (vrms)
LA75694M no.a0251-7/10 v14. frequency characteristics [fc] (1) apply dc voltage to the external agc if agc (pin 17) and adjust the voltage. (2) sg1 : 45.75mhz continuous wave 10mvrms sg2 : 45.65mhz to 39.75mhz continuous wave 2mvrms add the sg1 and sg2 signals using a t pat and adjust each sg signal level so that the above-mentioned levels are reached and input the added signals to the vif in. (3) first set the sg2 frequency to 45.65m hz, and then adjust the if agc voltage (v17) so that the output level at test point a becomes 0.5vp-p. v1 (4) set the sg2 frequency to 39.75mhz and measure the output level. v2 (5) calculate as follows : fc = 20log (db) v15.v16. differential gain, differential phase [dg, dp] (1) internal agc (2) fp = 45.75mhz apl50% 87.5% modulation video signal v i = 10mvrms (3) measure the dg and dp at test point a. v17. no-signal aft voltage [v 13 ] (1) internal agc (2) measure the dc voltage at the aft output (b). v18.v19.v20. maximum, minimum aft out put voltage, aft detection sensitivity [v 13 h, v 13 l, sf] (1) internal agc (2) fp = 45.75mhz 1.5mhz sweep = 10mvrms (vif input) (3) maximum voltage : v 13 h, minimum voltage : v 13 l. (4) measure the frequency deviation at which the voltage at test point b changes from v1 to v2. ? f v21.v22. vif input resistance, input capacitance [r i , c i ] (1) referring to the input impedance test circuit, measure r i and c i with an impedance analyzer. v2 v1
LA75694M no.a0251-8/10 v23.v24. apc pull-in range [fpu, fpl] (1) internal agc (2) fp = 39mhz to 51mhz continuous wave; 10mvrms (3) adjust the sg signal frequency to be higher than fp = 45.75mhz to bring the pll to unlocked state. note : the pll is assumed to be in unlocked stat e when a beat signal appears at test point a. (4) when the sg signal frequency is lowered, the pll is brought to locked state again. f1 (5) lower the sg signal frequency to bring the pll to unlock state. (6) when the sg signal frequency is raised, the pll is brought to locked state again. f2 (7) calculate as follows : fpu = f1 ? 45.75mhz fpl = f2 ? 45.75mhz v25. aft tolerance frequency 1 [ ? fa1] (1) internal agc (2) sg1 : 43.75mhz to 47.75mhz variable continuous wave 10mvrmns (3) adjust the sg1 signal frequency so that the aft output dc voltage (test point b) becomes 2.5v; that sg1 signal frequency is f1. (4) external agc (adjust the v17.) (5)apply 5v to the if agc (pin 17) and then pick up the vco oscillation frequency from gnd, etc.; and measure the fre quency f2 (6) calculate as follows : aft tolerance frequency : ? fa1 = f2 ? f1 (khz) v26.v27. vco maximum variable range (u, l) [dfu, dfl] (1) apply the v cc voltage to the external agc, if agc (pin 17). (2) pick up the vco oscillation frequency from the video output (a), gnd, etc. and adjust the vco coil so that the frequency becomes 45.75mhz. (3) fl is taken as the frequency when 1v is applied to the apc pin (pin 9). in the same manner, fu is taken as the frequency when 5v is applied to the apc pin (pin 9). dfu = fl?45.75mhz dfl = fl?45.75mhz v28. vco control sensitivity [ ] (1) apply the v cc voltage to the external agc, if agc (pin 17). (2) pick up the vco oscillation frequency from the vi deo output (a), gnd, etc. and adjust the vco coil so that the frequency becomes 45.75mhz. (4) f1 is taken as the frequency when 3.0v is applied to the apc pin (pin 9). in the same manner, f2 is taken as the frequency when 3.4v is applied to the apc pin (pin 9). = (khz/mv) v29. synchronization ratio [v s ] (1) internal agc (2) fp = 45.75mhz 87.5% 10step b/w v i = 10mvrms (3) measure the output amplitude at the measuring point a. vvideo (4) measure the pedestal voltage (dc) at the measuring point a. vped v s = (vped?v 6 tip) / vvideo 100 (%) f2?f1 400
LA75694M no.a0251-9/10 f1. 1st sif conversion gain [v g ] (1) internal agc (2) fp = 45.75mhz cw; 10mv (vif input) fs = 41.25mhz cw; 500 v (1st sif input) v1 (3) detection output level at test point c (vrms) v2 (4.5mhz) (4) vg = 20log db f2. 4.5mhz output level [s o ] (1) internal agc (2) fp = 45.75mhz cw; 10mv (vif input) fs = 41.25mhz cw; 10mv (1st sif input) v1 (3) detection output level at test point c (4.5mhz) s o (mvrms) f3. 1st sif maximum input [si max] (1) internal agc (2) fp = 45.75mhz cw; 10mv (vif input) fs = 41.25mhz cw; variable (1st sif input) (3) input level at which the detection output at test point c (4.5mhz) becomes s o 2db. si max f4.f5. 1st sif input resistance, input capacitance [r i (sif), c i (sif)] (1) using an input analyzer, measure r i and c i in the input impedance measuring circuit. c1. converter conversion gain [v g (sif)] (1) internal agc (2) fp = 45.75mhz cw; 10mv (vif input) fs = 41.25mhz cw; 316 v (1st sif input) (3) measure the 6mhz component at test point e (mix output) v1 (4) measure the 4.5mhz component at test point f (nicam output). v2 (5) v g (sif) = 20log db c2. sif converter maximum output level [v max] (1) internal agc (2) fp = 45.75mhz cw; 10mv (vif input) fs = 41.25mhz cw; 10mv (1st sif input) (3) measure the 6mhz component at test point e (mix output). v max (db v) c3. carrier suppression ratio [v gr (4.5)] (1) internal agc (2) fp = 45.75mhz cw; 10mv (vif input) fs = 41.25mhz cw; 316 v (1st sif input) (3) measure the 6mhz component at test point e (mix output). v 6 (db v) (4) measure the 4.5mhz component at test point e (mix output). v 4.5 (db v) (5) perform the following calculation. carrier suppression ratio v gr (4.5) (db) = v 6 ? v 4.5 c5. osc leakage [osc leak] (1) internal agc (2) fp = 45.75mhz cw; 10mv (vif input) fs = 41.25mhz cw; 316 v (1st sif input) (3) measure the 6mhz component at test point e (mix output). v 6 (db v) (4) measure the 500khz component at test point e (mix output). v 0.5 (db v) (5) perform the following calculation. carrier suppression ratio osc leak (db) = v 6 ? v 0.5 v2 v1 v1 v2
LA75694M ps no.a0251-10/10 note 1) unless otherwise speci fied for vif test, apply the v cc voltage to the if agc and adjust the vco coil so that oscillation occurs at 45.75mhz. 2) unless otherwise specified, the sw1 must be on. specifications of any and all sanyo semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. sanyo semiconductor co., ltd. strives to supply high-quality high-reliability products. however, any and all semiconductor products fail with some probability. it is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. in the event that any or all sanyo semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of sanyo semiconductor co., ltd. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equipment, refer to the "delivery specification" for the sanyo semiconductor product that you intend to use. information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. sanyo semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. this catalog provides information as of april, 2006. specifications and information herein are subject to change without notice.
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